1. Field of the Invention
The present invention relates to a chip design verifying and chip testing apparatus and method.
2. Description of Related Art
As electronic design automation (EDA) tools, which relates to a design automation and a design technique utilizing a hardware description language (HDL), are widely used in various electronic industrial fields, a design circumstance of an application specific integrated circuit (ASIC) has become greatly improved. For example, compared with the existing circuits having a capacity of from tens of thousands to hundreds of thousands of gates, recently circuits have been designed to have a capacity of millions of gates, and thus the ASIC design circumstance is improved enough to embody a system on a chip (SOC).
To embody such a circuit having a large-sized capacity on one ASIC element becomes possible due to a submicronized semiconductor process. As a semiconductor process becomes more submicronized, the ASIC element shows a tendency of a higher integration and a higher speed. In embodying a large-sized and complicated circuit on the ASIC element, one of the most troublesome cores relates to a verification of a proper operation of the designed circuit during a simulation and a system operation.
Since a circuit designer can estimate what the output results are for given inputs, a simulation is just a procedure confirming such a simple function without covering corner cases. When the designed circuit is mounted on a system board, the circuit on the system always does not generate inputs of the same form as inputs that are used to run a simulation for the function of the designed circuit. This is one of the greatest causes of the ASIC failure occurred when a simulation is sufficiently not performed.
As a circuit to be designed becomes complicated, and an intellectual property (IP) blocks to be recycled becomes increased in number, it becomes more difficult to make out a pattern of a simulation that can perfectly perform an operation of a chip on a system. Particularly, in case of a circuit having millions of gates, it requires much time to perform a simulation that is operated by a command language of a microprocessor.
In order to overcome the problems occurred during a simulation by using a hardware method other than a software method, a field programmable gate array (FPGA) that is re-programmable is widely used as a debugging means. As another solution for the problems, an ASIC verifier having a more effective debugging means and based on such an FPGA has been used. The FPGA is a device that a user runs a compile by using the user designed circuit as a compile input for the FPGA and downloads the result bit stream file to the FPGA, so that the user designed circuit is formed in the FPGA in the form of a hardware. The FPGA is generally used to effectively verify a relatively small-sized circuit, and thus an ASIC verifier of a high performance is required to effectively verify a relatively large-sized circuit.
As an example of a conventional chip design verifying apparatus, a computer built-in chip design verifier is disclosed in U.S. Pat. No. 6,009,256. The computer built-in chip design verifier includes a process for processing a software model of a chip to be designed in the computer and a re-configurable hardware board for embodying a hardware model to embody a chip and verifies an operation of an embodied chip. The computer built-in chip design verifier can organically be operated by connecting a target to which the designed chip will be applied to an external portion of the computer. However, as described above, the computer built-in chip design verifier includes a hardware board constructed with a field programmable gate array to embody a hardware model of the designed chip. Therefore, since it does not use a data compression method for a data transmission between a main memory of and a hardware board of a computer, a performance improvement is limited. In addition, as a hardware configuration of a circuit becomes complicated, a large number of hardware boards should be provided. Moreover, the computer built-in chip design verifier verifies an operation of a chip designed at a chip designing step but does not provide a function for testing an operation of the manufactured chip.
As another example of a conventional chip design verifier, a computer stand-alone chip design verifier is disclosed in U.S. Pat. No. 5,963,735. The computer stand-alone chip design verifier includes an emulator, a VLSI apparatus and a memory, outside a computer. The hardware emulator includes a configuration circuit, a logic analyzer/pattern generator, field programmable gate arrays, and an interface circuit. A design circuit and an application program are arranged in the computer. In order to embody a function of a circuit to be verified by performing a series of processing steps and a compile through an application program, bit stream files corresponding to each of the field programmable gate array are produced to respectively be written on the field programmable gate arrays. The user can control the hardware emulator using a software environment of an application program. The computer stand-alone chip design verifier includes field programmable gate arrays in order to embody a hardware model of a design to be verified.
As a graphic-related application example, the computer stand-alone chip design verifier should include an interface circuit or a separate interface circuit for an interface between the hardware emulator and a monitor for a screen output. In other words, since signals from the hardware emulator are outputted at a low speed, in case of directly displaying the signals on the monitor, a normal screen may be not outputted. Therefore, the interface circuit should be provided between the hardware emulator and the monitor to output a normal screen.
As described above, the conventional chip design verifiers have a problem in that a suitable hardware verifying environment should be provided additionally. That is, in case of a graphic-related design, additional graphic data buffering apparatus and a monitor to output a screen should be provided to monitor a screen output. Moreover, even though the conventional chip design verifiers can verify an operation of the designed chip, there comes a problem that it can not test an operation of the manufactured chip. Besides, the conventional chip design verifiers include standard means in themselves that can contain a design to be verified and focus on how to offer the results of the design to be verified to the standard means in a desirable manner, whereas they can not provide a proper window environment for an universal verification regarding how to effectively verify a design to be verified that is constructed with various functional blocks, according to each of the functional blocks, and how to effectively perform a debugging and to easily find errors.